1. Field of Invention
The present invention relates generally to semiconductor wafers, and more particularly to the devices and methods for fabricating wafers having solder bumps formed on one surface thereof.
2. Background
The desire for smaller, thinner, lighter electronic components has driven the semiconductor packaging industry to develop tools and processes for wafer backside thinning by grinding and polishing before the wafers are diced into chips. As packaging assemblers develop more sophisticated multi-chip packages containing multiple die which are often stacked in a 3D assembly, the need for thinner die becomes more acute.
Wirebond stacked die packages may contain die thinned to less than 200 um, with even more aggressive thinning anticipated in the future. Because the surface of a wafer being processed for wire bonded interconnects is planar, the mechanical process of backside grinding and surface finishing is capable of removing greater than 90% of the original wafer thickness without breakage or lattice damage. These techniques have enabled the manufacture of extremely thin stacked wirebond package assemblies for advanced electronics.
With increasing semiconductor complexity comes the desire for greater signal bandwidth, which requires that the semiconductor chips have higher interconnect density from the die to the module substrate, or in the case of stacked assemblies, from die to die. Higher performance interconnects are achieved by switching from wirebond to solder bump connections. However, since the solder bumping process must be done with unthinned wafers, the 30-100 um solder bump feature creates significant challenges to obtain wafer backside thinning comparable to what is achieved today for wirebond wafers.
Thinning of wafers with solder bumps is done today by using a compliant tape on the wafer front side to conform around, cushion, and protect the solder bumps during the grinding process. This is reasonably effective for final wafer thicknesses greater than 300 um. For thinner dimensions, a tape with higher compliancy allows for replication of the underlying bump features especially in dissimilar pattern density regions of the bumps. Conversely, a tape with lower compliancy may also reflect pattern density differences as well as posing difficulty in removal. These issues have prevented the packaging industry from embracing thin single and multi-chip stacked die packaging for solder bumped wafers.
3. Objects and Advantages
It is therefore a principal object and advantage of the present invention to provide a fabrication device and method for permitting the effective thinning of bumped wafers through a grinding operation.
It is another object and advantage of the present invention to provide a fabrication device that permits backside grinding of bumped wafers to thinner dimensions than is presently feasible.
It is a further object and advantage of the present invention to provide a fabrication device that is easily adapted to existing fabrication processes.
Other objects and advantages of the present invention will in part be obvious, and in part appear hereinafter.